(1) Field of the Invention
The present invention relates to non-volatile semiconductor memories and a data erasing method for the same, and more particularly to a non-volatile semiconductor memory which comprises memory cells constituted by field-effect transistors capable of setting electrical threshold voltage and is capable of making flash erasing, and a data erasing method for the same.
(2) Description of the Related Art
Non-volatile semiconductor memories, which comprise an array of a plurality of memory cell transistors constituting memory cells and capable of electrically setting threshold voltage setting, such as field-effect transistors with floating gates, have been attracting attention as flash memories capable of making electrical flash erasing of data.
An example of such non-volatile semiconductor memory is shown in FIG. 1.
This non-volatile semiconductor memory comprises a memory cell array 1, a plurality of word lines WL1 to WLm, a plurality of digit lines DL1 to DLn, a source line SL, a source potential supply circuit 6, an X-decoder 2 and a word line potential supply circuit 3x, a Y-decoder 4 and a Y-selector 5, a sense amplifier 8, a reference current generator 9, and a drain potential supply circuit 7.
The memory cell array 1 includes a plurality of memory cell transistors MC11 to MCmn arranged in rows and columns. Each memory cell transistor is a field-effect transistor having a floating gate and capable of electrically setting a threshold voltage. Each of the word lines WL1 to WLm is provided for each row of the array of memory cell transistors MC11 to MCmn and connected to the control gate of each of the memory cell transistors in the corresponding row. Each of the digit lines DL1 to DLn is provided for each column of the array of memory cell transistors MC11 to MCmn and connected to the drain of each of the memory cell transistors in the corresponding column. The source line SL is connected to the source of each of the memory cell transistors MC11 to MCmn. The source potential supply circuit 6 is operable according to an erasing control signal ER such that it supplies a predetermined erasing voltage Ve to the source line SL at the time of flash erasing operation and that it holds the source line SL at ground potential when the flash erasing operation is not taking place. The X-decoder 2x and word line potential supply circuit 3x operate together according to control signals AXS, AXN and VX and an address signal ADX so as to select one of the word lines WL1 to WLm to be held at a selected level, i.e., the level of supply potential Vcc in normal read operation, hold all word lines WL1 to WLm at the ground potential level in the flash erasing operation and select one word line to be held at a write voltage Vx in write operation. The Y-decoder 4 and Y-selector 5 operate together according to control signals AYN and AYS and an address signal ADY so as to select one of the digit lines DL1 to DLn in the normal read and write operations and bring all the digit lines DL1 to DLn to be in a non-selective floating state in the flash erasing operation. The sense amplifier 8 compares, in the read operation, the current flowing in the digit line selected by the Y-decoder 4 and Y-selector 5 with a reference current Ir to check whether a selected memory cell transistor connected to the selected digit line is "on" (so that the selected digit line current is higher than the reference current Ir) or "off". The drain potential supply circuit 7 supplies a predetermined write potential to the digit line selected by the Y-decoder 4 and Y-selector 5.
In this non-volatile semiconductor memory, the X-decoder 2x includes an inverter IV21 corresponding to each bit of the X-address signal ADX, and NAND type logical gates G21 and G22, a NAND type logical gate G23 corresponding to each word line, and transistors Q21 to Q23. The Y-decoder 4 has a structure similar to that of the X-decoder 2x. The Y-selector 5 includes transistors Q51 to Q5n which receive the output signals of the Y-decoder 4 respectively at their gates. The sense amplifier 8 is of a current comparator type including inverters IV81 and IV82 and transistors Q81 and Q88.
The operation of this non-volatile semiconductor memory will now be described.
In the normal write operation, the control signals AXS and AXN are set to high level to select one word line according to the X-address signal ADX and supply the write voltage Vx to the selected word line from the word line potential supply circuit 3x. Also, the control signals AYS and AYN are set to high level to select one digit line according to the Y-address signal and supply a write voltage Vp to the selected digit line from the write drain potential supply circuit 7. At this time, the source line SL is held at ground potential by the source potential supply circuit 6. As a result, the predetermined write voltages Vx and Vp are applied to the control gate and drain of the memory cell transistor which is connected to the selected word line and the selected digit line to increase the threshold voltage of this memory cell transistor. For example, the threshold voltage is increased beyond the supply potential Vcc, when the control gate potential is made Vcc in the read operation.
In the read operation, one word line is selected according to the X-address signal ADX to be held at a selected level, i.e., the supply potential Vcc. Also, one digit line is selected according to the Y-address signal ADY to be connected to the sense amplifier 8. The sense amplifier 8 compares the current flowing in the selected digit line with the reference current Ir. When the selected memory cell transistor is in the write state, its threshold voltage is higher than the selected level (Vcc) of the selected word line. In this case, no drain current of the selected memory cell transistor flows, that is, no current is caused to flow to the selected digit line. The sense amplifier 8 thus determines that this memory cell transistor is "off". When the selected memory cell transistor is in an erasing state, its threshold voltage is lower than the selected level of the selected word line, and its drain current is higher than the reference current Ir. The sense amplifier 8 thus determines that this memory cell transistor is "on".
In the erase operation, the control signal AXN is set to a low level to turn on the transistors Q23 so as to hold all the word lines WL1 to WLm at the ground potential. Also, the control signal AYN is set to a low level to turn off all the transistors Q51 to Q5n so as to hold all the digit lines DL1 to DLn in the non-selective state, i.e., the floating state. In this state, the erasing voltage Ve of a predetermined high potential, is supplied to the source line SL from the source potential supply circuit 6. As a result, the threshold voltage of all the memory cell transistors MC11 to MCmn becomes lower than a predetermined voltage resulting in the flash erasing state.
Such flash erasing is subject to fluctuations of its progress speed due to such causes as memory cell transistor gate insulating film thickness fluctuations. The flash erasing operation, therefore, may result in the generation of some over-erased memory cell transistors. The over-erased memory cell transistor is such that it is turned on (with its threshold voltage becoming negative) although its word line is at the non-selected level (for instance, a ground potential). In such a case, the digit line to which the over-erased memory cell transistor is connected, carries an "on" cell current at all times to disable normal data reading.
Accordingly, in this non-volatile semiconductor memory, after the end of the flash erasing operation all the digit lines DL1 to DLn are selected by setting the control signals to AYS and AYN to low and high levels, respectively, while setting all the word lines WL1 to WLm to the non-selected level, i.e., ground potential level, by setting the control signal AYN to low level, and the currents in all the digit lines DL1 to DLn are compared to the reference current Ir to check whether the memory cell transistors MC11 to MCmn include even a single "on" state memory cell transistor (over-erased cell). When even a single "on" state memory cell transistor is detected, shallower writing than the normal writing, that is, writing to obtain a smaller memory cell transistor threshold voltage change than in the normal writing, is done with respect to all the memory cell transistors MC11 to MCmn, thus restoring the over-erased memory cell transistor or transistors to the normal erased state (as disclosed, for instance, in Japanese Patent Application Kokai Publication No. Hei 4-222994).
In the above case, all the digit lines DL1 to DLn are selected and checked for any "on" state (or over-erased) memory cell transistors MC11 to MCmn. Instead, it is possible to adopt a digit line unit detection method, in which a single digit line is selected according to the Y-address signal ADY by setting both the control signals AYS and AYN to high level to check for any "on" one or ones among the memory cell transistors connected to the selected digit line.
In the prior art non-volatile semiconductor memory described above, after the flash erasing operation, a check is made, by selecting all the digit lines or a single digit line, for any over-erased memory cell transistor connected to any of the selected digit lines or to the single selected digit line and, when an over-erased memory cell transistor is detected, shallow writing compared to the normal writing is done with respect to the memory cell transistors connected to all the digit lines or to the single selected digit line. By doing the shallow writing, the over-erased memory cell transistor can be restored to the normal erased state. However, some memory cell transistors, to which the shallow writing has been done, may be found in the vicinity of a criteria for the judgment of the erased state. These memory cell transistors may go beyond the criteria to be in the non-erased state. To preclude this possibility, it is necessary to check the erased state again, and when a memory cell transistor in the non-erased state is detected, it is necessary to repeat operation from the flash erasing. This means extra time is required until all the memory cell transistors are restored to the normal erased state.
Besides, even when no memory cell transistor in the non-erased state is detected as a result of the confirmation of the erased state after the shallow writing, the shallow writing increases the threshold voltage of all the memory cell transistors, thus reducing the drain current in the read operation so as to reduce the speed thereof.